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Verilog: KNOWNBUG test for property ... endproperty #932

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Jan 16, 2025
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@kroening kroening commented Jan 16, 2025

The type checker uses the wrong fragement of the expression syntax for property ... endproperty.

Replicates #931.

@kroening kroening marked this pull request as ready for review January 16, 2025 15:35
The type checker uses the wrong fragement of the expression syntax for
property ...  endproperty.

Replicates #931.
@tautschnig tautschnig merged commit bc7a3df into main Jan 16, 2025
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@tautschnig tautschnig deleted the property1 branch January 16, 2025 19:52
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